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ADuC7060
MEMORY MAPPED REGISTERS
0xFFFFFFFF
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers, except the core registers, reside
in the MMR area. All shaded locations shown in Figure 11 are
unoccupied or reserved locations and should not be accessed by
user software. Figure 11 shows the full MMR memory map.
The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA buses: advanced high performance bus (AHB) used
for system modules and advanced peripheral bus (APB) used
for a lower performance peripheral. Access to the AHB is one
cycle, and access to the APB is two cycles. All peripherals on the
ADuC7060 are on the APB except the Flash/EE memory, the
GPIOs, and the PWM.
0xFFFF0FC0
0xFFFF0F80
0xFFFF0E24
0xFFFF0E00
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF0948
0xFFFF0900
0xFFFF0730
0xFFFF0700
0xFFFF0620
0xFFFF0600
0xFFFF0570
0xFFFF0500
0xFFFF0490
0xFFFF048C
0xFFFF0470
0xFFFF0450
0xFFFF0420
0xFFFF0404
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0238
0xFFFF0220
0xFFFF0140
0xFFFF0000
PWM
FLASH CONTROL
INTERFACE
GPIO
SPI
I 2 C
UART
DAC
ADC
BAND GAP
REFERENCE
SPI/I 2 C
SELECTION
PLL AND OSCILLATOR
CONTROL
GENERAL-PURPOSE
TIMER
WATCHDOG
TIMER
WAKE-UP
TIMER
GENERAL-PURPOSE
TIMER
REMAP AND
SYSTEM CONTROL
INTERRUPT
CONTROLLER
Figure 11. Memory Mapped Registers
Rev. 0 | Page 23 of 100
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